• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Method and device for reliably transmitting data to at least one equipment (23) in which: From its initial clock H1, a device (23) generates at least a first clock H1U from a rising edge of the initial clock H1 with a frequency F1U and a second clock H1D from a falling edge of the initial clock Hi, with a frequency F1D, The equipment: Reads received data using at least a first rising edge of H1U and a consecutive falling edge of the first rising edge of H1U, then reads the received data using a first rising edge of H1D and a consecutive falling edge of the first rising edge of H1D , the four clock edges used being consecutive by 2F1, Decode at least the four messages using an error correcting code, When at least one decoded message is correct, it uses the information contained in this message to control a device in connection with said equipment item.
    公开号:FR3087975A1
    申请号:FR1801150
    申请日:2018-10-31
    公开日:2020-05-01
    发明作者:Damian ANDRADE ALFONSECA；Tony TEIXEIRA；Stephane Guguen
    申请人:Thales SA；
    IPC主号:
    专利说明:

    [0001] METHOD AND SYSTEM FOR RELIABLE DATA TRANSMISSION The invention relates to a method for reliably transmitting data, ensuring that on reception the data matches the transmitted data.
    It is particularly applicable for transmitting data in a system comprising several synchronous devices, the clocks of which may exhibit a drift.
    The method can be used in systems which must simultaneously supply power to a rotating machine.
    In the case of simultaneous information transmission, reliability in data transmission is essential to ensure proper functioning of the system.
    When the simultaneous transmission of data between several pieces of equipment is necessary to ensure this reliability, it is known to use a communication bus to transmit the data and a bus to transmit a clock to synchronize the transmission of the data.
    FIG. 1A schematizes this type of architecture with a transmission line for the data D and the use of a dedicated clock CLK 20 to synchronize the transmission.
    This requires the installation of additional wiring.
    In the case of devices which are not synchronized by a clock common to the different devices (without a distributed clock), the devices must have the same operating frequency and a tolerance on the clocks of each restricted device, in order to avoid a Too great a drift in the time of reception of data on each of the devices.
    In this case, as shown diagrammatically in FIG. 1B, an offset (phase shift) between the transmission clock CLK-rx of the data and the reception clock CLKRx of the data may appear.
    In general, the rising or falling edge of the clock of the receiving equipment is used to ensure that the data is read correctly.
    2 On the other hand, during data transmission, disturbances on the transmission line can cause a false bit to be read, which can lead to incorrect detection of a start bit for reading.
    In this case, the reading of the message is incorrect.
    If the system includes a CRC type correction means, the message will simply be rejected.
    The system can then repeat the transmission of the message until a good result is obtained.
    This method has the drawback of reducing the useful bandwidth.
    The idea of the present invention is based on a new approach for reading data which makes use in particular of selected and consecutive clock edges of two clocks generated from a first initial clock operating at a frequency value at least equal to twice the data transmission frequency.
    The invention relates to a method for reliably transmitting data to at least one device provided with an initial clock H1 in a system comprising at least one message sending device working with a first clock Ho characterized in that it comprises at least minus the following steps: From its initial clock H1, at an initial frequency F1, a device 20 generates at least a first clock Hju from a rising edge of the initial clock with a frequency Fis and a second clock Hm at From a falling edge of the initial clock H1, with a frequency Fm, the device then performs the following steps: Read the data received using at least a first rising edge of the first clock Hlu and a consecutive falling edge of the first rising edge of the first generated clock Hie, then read the received data using a first rising edge of the second clock KID and a consecutive falling edge of the first st rising edge of the second generated clock Hm, the four clock edges used being consecutive 30 of 2F1, 3 Decode at least the four messages using an error correcting code, When at least one message is decoded correctly, use the information contained in this message to control a device in connection with the said equipment item (s).
    The control can be a regulation in the operation of a device.
    The data communication is done, for example, using a communication protocol implementing a CRC type correction.
    The values of the frequencies are, for example, defined as follows: F1 Fo -2 = FIE = FlD = FO ± -No with Fo the initial frequency corresponding to the sending equipment and No the number of bits of the message.
    The method according to the invention is implemented for inverters 15 supplying energy to a rotating machine, in a synchronized manner.
    The invention also relates to a system for transmitting data reliably to at least one item of equipment configured to control a device, the system comprising a device having a clock Ho operating at a frequency Fo characterized in that an item of equipment 20 comprises at least the following elements: A clock generator module configured to generate from the initial clock H1 of the equipment, at an initial frequency F1, at least one first clock Hu, from a rising edge of the clock initial H1, with a frequency Fiu and a second clock H1D from a falling edge of the initial clock H1, with a frequency Flo, A data processing module configured to: read the data received using at least one first rising edge of the first clock Hiu and a consecutive falling edge of the first rising edge of the first generated clock Hiu, then read the received data 4 using a first rising edge of the second th clock Hep and a consecutive falling edge of the first rising edge of the second generated clock Hm, the four clock edges used being consecutive from 2F1, and decode at least the four messages using an error correcting code 5, If the verification of the message with the CRC is correct, use the information contained in the message to generate a control signal to a device in connection with the said equipment (s).
    The data sender device is configured, for example, to use a communication protocol having a CRC error corrector.
    The data transmitter device is linked with several inverters configured to generate energy, synchronously, and supply said energy to a rotating machine.
    Other characteristics and advantages of the present invention will emerge better on reading the description of exemplary embodiments given by way of illustration and in no way limiting, appended to the figures which represent: FIG. 1A, an illustration of the use of a dedicated clock for reading data and FIG. 1B, the use of two clocks according to the prior art, - Figure 2, an example of implementation of the invention, - Figure 3, a diagram illustrating the generation of two clocks according to the method of the invention, and - Figure 4, an example of a timing diagram for reading data using the method according to the invention.
    In order to better understand the method according to the invention, the example which follows is given by way of illustration and in no way limiting for a system comprising several inverters which are configured to supply power (energy) to a rotating machine, such as it is shown in figure 2.
    These inverters must be able to supply power simultaneously, in order to avoid power returns through the wires which could be harmful to operation, and on the contrary to have an accumulation of energy.
    In FIG. 2 for reasons of simplification, only the detail of the link of an inverter equipment item has been shown.
    FIG. 2 comprises a device 20 for transmitting data D, comprising at least one clock Ho operating at a frequency Fo and a data transmission module 21.
    The data D contained in a message M are transmitted by means of a communication protocol, known to those skilled in the art and which will not be detailed, to a device 23 such as an inverter configured, for example, to generate energy at the level of a rotating machine 30.
    The equipment configured to generate energy comprises an HR clock, a generator module 24 of two Rio clocks, Hiu, from a first initial clock H1, a module for receiving the message 25, a data processing module. 26, such as a processor, which will process the data received at the rate of the two clocks, using clock edges according to the steps of the method according to the invention described below, in order to determine the data or data correctly read or decoded.
    These data will be used by an energy generator module 27 to transmit power upon receipt of a control signal to the rotating machine 30.
    FIG. 3 illustrates an example for the generation of the two clocks obtained from the initial operating clock of a device and which will be used for reading the data received by the device.
    300 Clock of the transmitting device at a frequency Fo 301 Clock of the receiving device at an initial frequency F1 302 Clock generated on the rising edges at a frequency F1u 303 Clock generated on the falling edges at a frequency F10 The generation module d the clock considers the initial clock H1 of the receiver module of the equipment and generates: 6 - a first clock Hiu by considering a first rising edge 310 of the initial clock H1 to generate a first rising edge 320 of the first clock Hiu, a second rising edge 312 of the initial clock H1 to generate a first falling edge 321 5 with a frequency Fiu, - a second clock H1 ^ considering a first falling edge 311 of the initial clock H1 to generate a first rising edge 330 of the second clock H1 ^, a second falling edge 313 of the initial clock H1 to generate a first falling edge 331 of the second clock H1 ^ with a frequency F1 ^.
    FIG. 4 illustrates the sequencing of the reading of data from the two clocks Hiu and H1D.
    The transmitting equipment of the data transmitting device sends a data message D, 400, of a size of No bits at a frequency Fo, 15 300.
    The transmission can be done using a communication protocol known to those skilled in the art, implementing a method for verifying the transmission of data of CRC (Cyclic Redondancy Check) type, for example.
    The initial clock H1 of the receiver module of the equipment 20 operates at a frequency F1, 301 and made it possible to generate a first clock Hiu, 302, and a second clock H1 ^, 303, as was explained previously in FIG. 3.
    The frequency F1 is equal to 2F0 with an error <2 L.
    The data will be read using the two generated clocks 25 of frequency Fiu and F1D respectively and by using two consecutive edges of the first clock Hiu and two consecutive edges of the second clock FH1D (four consecutive edges).
    Thus the reading is performed on a rising edge of 111u, followed by a falling edge of H1D, at a frequency Fui, followed by a rising edge of H1D, followed by a falling edge of 30 H1D at a frequency Fr ) with the relations: 7 F, Fo 7 = Fui = FlD FO ± No In the example given by way of illustration, the frequency is 1 Hz therefore with a period of 1s.
    The number of bits to be transmitted is eight.
    So the maximum offset tolerated for the clocks is 1/8 = 0.125 s.
    The tolerance required will depend on the size of the message.
    5 The receiver reads the message according to the four successive edges: On the rising edge of Hiu, 441, M1 data received, 451, On the falling edge of Hiu, 442, M2 data received 461, On the rising edge of HiD 443, M3 data received, 471, On the falling edge of H1D, 444, M4 data received 481.
    The four readings M1, M2, M3 and M4 are transmitted to the data processing module which will use an error correction method, for example a CRC code, in order to determine the correct message (s).
    When at least one of the four messages is correct, then the processing module deduces that the original message transmitted is disturbed.
    In this case, it does not take the decoded message into account and will start a cycle of reading and decoding the message again until correct decoding is obtained.
    In the case where at least one message is decoded correctly (correct decoded message corresponding to a reliable message), after application of a correct CRC error code, then the processing module considers that the message is reliable, the The data contained are also reliable and can be used for controlling a device.
    In the case of the application of generating power to a rotating machine, synchronization is thus ensured in the transmission of the control signal from the energy-emitting equipment to the rotating machine and thus backcurrent is avoided via connecting lines between the various pieces of equipment that can be harmful to the proper functioning of the machine, or even damage it.
    The method according to the invention advantageously makes it possible to read the message by detecting any errors, without using a dedicated clock line.
    The tolerance between the clocks of each device in the system has no impact
    权利要求:
    Claims (7)
    [0001]
    CLAIMS 1 - Method for reliably transmitting data to at least one equipment item (23) provided with an initial clock H1 in a system comprising at least one message sending device (20) working with a first clock Ho characterized in that ' it comprises at least the following steps: From its initial clock H1, at an initial frequency F1, a device (23) generates at least a first clock Hiu from a rising edge of the initial clock H1 with a frequency Fiu and a second clock H1D from a falling edge of the initial clock H1, with a frequency FiD. The device then performs the following steps: Read the data received using at least a first rising edge of the first clock Hiu and a consecutive falling edge of the first rising edge of the first generated clock Hlu, then read the received data using a first rising edge of the second clock H1D and a consecutive falling edge of the first rising edge of the second generated clock H1D, the four clock edges used being consecutive from 2F1, Decode at least the four messages using an error correcting code When at least one message is decoded correctly, use the information contained in this message to control a device in connection with said equipment or devices.
    [0002]
    2 - Method according to claim 1 characterized in that the data communication is done using a communication protocol implementing a CRC type correction. 10
    [0003]
    3 - Method according to one of claims 1 or 2 characterized in that the values of the frequencies are defined as follows: F1 Fo = Fiu - ElD = FO ± No With Fo the initial frequency corresponding to the transmitting equipment and NO the number of bits of the message. 5
    [0004]
    4 - Method according to one of claims 1 to 3 characterized in that the equipment is inverters supplying energy to a rotating machine (30). 10
    [0005]
    5 - System for reliably transmitting data to at least one item of equipment (23) configured to drive a device (30), the system comprising a device (20) having a clock Ho operating at a frequency Fo characterized in that a equipment (23) comprises at least the following elements: A clock generator module (24) configured to generate from the initial clock H1 of the equipment (23), at an initial frequency F1, at least a first clock Hiu from a rising edge of the initial clock H1, with a frequency Fiu and a second clock H10 from a falling edge of the initial clock H1, with a frequency F10, 20 A module for processing data (26) configured to: Read the received data using at least a first rising edge of the first clock Hiu and a consecutive falling edge of the first rising edge of the first generated clock Hiu, then read the received data using a first edge amount of l a second clock Hm and a consecutive falling edge of the first rising edge of the second generated clock Rip, the four clock edges used being consecutive from 2F1, and decode at least the four messages using an error correcting code, 11 If the verification of at least one message with the CRC is correct, use the information contained in the message to generate a control signal to a device in connection with the said equipment (s). 5
    [0006]
    6 - System according to claim 5 characterized in that the data transmitter device (20) is configured to use a communication protocol having a CRC error corrector.
    [0007]
    7 - System according to one of claims 5 or 6 characterized in that the 10 data transmitter device (20) is in connection with several inverters (23) configured to generate energy and supply said energy to a rotating machine.
    类似技术:
    公开号 | 公开日 | 专利标题
    EP3648382A1|2020-05-06|Method and system for reliable data transmission
    CN103582112B|2018-02-16|A kind of time advance method for determination of amount, user equipment and base station
    CN101601221B|2012-06-13|Apparatus, methods for providing limited use of zadoff-chu sequences in pilot or preamble signals
    JP2578334B2|1997-02-05|Digital transmission method
    FR2495872A1|1982-06-11|ASSEMBLY AND METHOD FOR PROCESSING TELEVISION VIDEO DATA
    EP0409230B1|1995-09-27|Phase matching circuit
    FR2587570A1|1987-03-20|ADAPTIVE COMMUNICATION SYSTEM
    FR2505114A1|1982-11-05|TELEVISION VIDEO DATA PROCESSING SYSTEM
    JP2005354310A|2005-12-22|Device and method for data transmission and device and method for data reception
    MX2010013172A|2010-12-21|System and method of an in-band modem for data communications over digital wireless communication networks.
    US20120185721A1|2012-07-19|Multi-rate sampling for network receiving nodes using distributed clock synchronization
    CN102804665A|2012-11-28|System And Method For Supporting Higher-layer Protocol Messaging In An In-band Modem
    CN111602351A|2020-08-28|More efficient use of single channel receivers for receiving multi-channel transmissions
    FR2539935A1|1984-07-27|IMPROVED COLLISION DETECTION METHOD
    EP0080481B1|1984-10-24|Method and device for the asynchronous series communication of the multipoint type between a plurality of logic transceivers
    US7664144B2|2010-02-16|Packet-switched network synchronization system and method
    EP1413494A1|2004-04-28|Method for secure exchange of information messages
    EA005608B1|2005-04-28|Synchronisation method for the uplink channel in a point-to-multipoint communication with ofdm modulation
    JP3412558B2|2003-06-03|Clock frequency control method and receiving device used therefor
    EP0028188B1|1986-09-24|Beacon system for stage-by-stage transmission of information
    US4910755A|1990-03-20|Regenerator/synchronizer method and apparatus for missing-clock timing messages
    JP2019068296A|2019-04-25|Information processing device, control method thereof, and computer program
    JP2005005889A|2005-01-06|Communication system and communication method
    EP0594402A2|1994-04-27|Apparatus for and method of clock timing recovery in a receiver
    JPH08256164A|1996-10-01|Communication system
    同族专利:
    公开号 | 公开日
    US10862665B2|2020-12-08|
    CA3060527A1|2020-04-30|
    EP3648382A1|2020-05-06|
    FR3087975B1|2021-12-03|
    US20200136794A1|2020-04-30|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US5600662A|1993-09-21|1997-02-04|Cirrus Logic, Inc.|Error correction method and apparatus for headers|
    US5687193A|1995-06-22|1997-11-11|France Telecom|Manchester coder/decoder|
    EP0805574A1|1996-04-30|1997-11-05|Motorola, Inc.|Method for generating a clock signal for use in a data receiver, clock generator and remote controlled access system for vehicles|
    US20050081129A1|2003-10-08|2005-04-14|Shah Paras A.|Bus device that concurrently synchronizes source synchronous data while performing error detection and correction|
    WO2014116931A1|2013-01-24|2014-07-31|Texas Instruments Incorporated|Signal conditioner|
    US5450458A|1994-08-05|1995-09-12|International Business Machines Corporation|Method and apparatus for phase-aligned multiple frequency synthesizer with synchronization window decoder|
    US5835753A|1995-04-12|1998-11-10|Advanced Micro Devices, Inc.|Microprocessor with dynamically extendable pipeline stages and a classifying circuit|
    US5867533A|1996-08-14|1999-02-02|International Business Machines Corporation|Digital delta mode carrier sense for a wireless LAN|
    TW459229B|1999-02-24|2001-10-11|Matsushita Electric Ind Co Ltd|Semiconductor memory device|
    KR100546389B1|2003-10-22|2006-01-26|삼성전자주식회사|Semiconductor memory device having different synchronizing timing according to CL|
    US7098714B2|2003-12-08|2006-08-29|Micron Technology, Inc.|Centralizing the lock point of a synchronous circuit|
    US7681099B2|2007-05-17|2010-03-16|Advanced Micro Devices, Inc.|Techniques for integrated circuit clock signal manipulation to facilitate functional and speed test|
    US8005995B2|2007-08-16|2011-08-23|Micron Technology, Inc.|Command interface systems and methods|
    JP2009181439A|2008-01-31|2009-08-13|Toshiba Corp|Memory system|
    US8371669B1|2009-02-18|2013-02-12|Marvell International Ltd.|Fire timing control in printing devices|
    KR101220178B1|2009-10-28|2013-01-11|한국전자통신연구원|Symbol synchronization apparatus and method of a passive RFID reader|
    US8983413B2|2010-12-01|2015-03-17|Intel Mobile Communications GmbH|Communication device including multiple LO receivers|
    GB2499699A|2011-12-14|2013-08-28|Wolfson Ltd|Digital data transmission involving the position of and duration of data pulses within transfer periods|
    US10180874B2|2015-10-28|2019-01-15|Western Digital Technologies, Inc.|Storage device operations based on bit error rate estimate|JP2019191070A|2018-04-27|2019-10-31|セイコーエプソン株式会社|Resampling circuit, physical quantity sensor unit, inertia measuring device, and structure monitoring device|
    JP2019191069A|2018-04-27|2019-10-31|セイコーエプソン株式会社|Resampling circuit, physical quantity sensor unit, inertia measuring device, and structure monitoring device|
    法律状态:
    2019-09-27| PLFP| Fee payment|Year of fee payment: 2 |
    2020-05-01| PLSC| Publication of the preliminary search report|Effective date: 20200501 |
    2020-10-13| PLFP| Fee payment|Year of fee payment: 3 |
    2021-09-30| PLFP| Fee payment|Year of fee payment: 4 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1801150A|FR3087975B1|2018-10-31|2018-10-31|METHOD AND SYSTEM FOR RELIABLE DATA TRANSMISSION|FR1801150A| FR3087975B1|2018-10-31|2018-10-31|METHOD AND SYSTEM FOR RELIABLE DATA TRANSMISSION|
    EP19205919.4A| EP3648382A1|2018-10-31|2019-10-29|Method and system for reliable data transmission|
    CA3060527A| CA3060527A1|2018-10-31|2019-10-29|Method and system for transmitting data reliably|
    US16/667,455| US10862665B2|2018-10-31|2019-10-29|Method and system for transmitting data reliably|
    [返回顶部]